Seminář ÚFKL: Manus Hayne

Ústav fyziky kondenzovaných látek vás zve na přednášku

Manus Hayne (Lancaster University, UK): ULTRARAM: A High-performance, Ultra-efficient, Non-volatile, Random-access Memory

Professor Manus Hayne
Department of Physics, Lancaster University, Lancaster LA1 4YB, United Kingdom

Abstrakt:

With 2019 sales of $106 bn, memories are (almost) equally matched with logic in terms of the market size.1 However, in contrast to logic, which is a monolith of a single technology, Si CMOS, there are four ‘conventional’ memories, SRAM, DRAM, NAND and NOR flash, only one of which (SRAM) has CMOS as its fundamental basis. Furthermore, there is vibrant research activity into new forms of memory, usually called emerging memories, including phase change RAM, resistive RAM, and spin-transfer torque magnetic RAM.2,3 These emerging memories aspire to combine the non-volatility of flash with the performance of DRAM, and some are available commercially, e.g. OptaneTM. With this in mind, there is clearly scope for
innovative memory research, and realistic prospects of commercialisation.

In this talk I will introduce a novel charge-based memory,4 ULTRARAMTM, which exploits the ability of a triple-barrier resonant tunnelling (TBRT) structure to switch from opaque to transparent on application of ≤2.5 V, allowing a memory that combines the contradictory properties of non-volatility (flash-like) with fast, low-energy switching (DRAM-like).5,6 The talk will be divided into four parts. In the first part I will briefly introduce the research environment in Lancaster and my team. In Part II I will explain the physics behind the TBRT concept and describe the results of first generation (Gen I) devices. Part III will then go on to present the further innovations that resolve issues in Gen I devices, and allow the implementation
of a highly compact architecture suitable for arrays. Part IV details planned research to allow large-volume manufacture of ULTRARAMTM memory chips; large arrays, development and integration of III-V CMOS for addressing, implementation on Si substrates and device scaling.


1 Semiconductor Industry Association https://www.semiconductors.org/
2 S. Yu, S., & Chen, P.-Y., 2016. Emerging Memories Technologies – Recent Trends and Prospects, IEEE Solid-State Circuits Magazine (Spring issue) 2016, pp. 43-56. https://doi.org/10.1109/MSSC.2016.2546199
3 Prall, K., 2017, Benchmarking and Metrics for Emerging Memories, 2017 IEEE International Memory Workshop (IMW), Monterey, 2017, pp. 1-5. https://doi.org/10.1109/IMW.2017.7939072
4 Hayne, M., 2019. Electronic Memory Devices, US10243086B2 https://patents.google.com/patent/US20170352767A1/en
5 Tizno, O., Marshall, A.R.J., Fernández-Delgado, N., Herrer, M., Molina S.I., & Hayne, M., 2019. Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cells, Scientific Reports 9, 8950. https://doi.org/10.1038/s41598-019-45370-1
6 Lane, D., & Hayne, M., 2020. Simulations of Ultralow-Power Nonvolatile Cells for Random-Access Memory, IEEE Trans. Electron Devices 67, pp 474-480. https://doi.org/10.1109/TED.2019.2957037

 

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